1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection device, and more particularly, to a silicon controlled rectifier (SCR) device for ESD protection.
2. Description of the Prior Art
For integrated circuits, ESD damage is a critical issue, and many types of ESD protection devices such as diode, MOS transistor, bipolar transistor, and SCR device have been proposed to deal with ESD damage. When an ESD pulse occurs, the ESD protection device needs to be turned on in advance and grounding the ESD current so that the internal circuits to be protected are not damaged. Among various ESD protection devices, SCR device has been broadly used because of its low holding voltage in comparison with other ESD protection devices.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional lateral silicon controlled rectifier (LSCR) device. As shown in FIG. 1, the LSCR device includes a p type substrate 10, a first n+ doped region 12 formed in the substrate 10, a p+ doped region 14 formed in the substrate 10, a second n+ doped region 16 formed in the substrate 10, and an n well 18 disposed underneath the first n+ doped region 12 and the p+ doped region 14. The first n+ doped region 12, the p+ doped region 14, and the second n+ doped region 16 are arranged laterally in the substrate 10 and isolated form each other by shallow trench isolations 20. The first n+ doped region 12 and the p+ doped region 14 are electrically connected to an anode 22, and the second n+ doped region 16 is electrically connected to a cathode 24.
When the LSCR is triggered, the ESD current flows through the p+doped region 14, the n well 18, the P type substrate 10, the second n+ doped region 16, and then to ground. However, the trigger voltage of this type of conventional LSCR device is normally greater than 10 V, which is too high to protect the internal circuit in many applications.
Please refer to FIG. 2. FIG. 2 is a schematic diagram of another conventional LSCR device. As shown in FIG. 2, the LSCR device includes a p type substrate 30, a first n+ doped region 32 formed in the substrate 30, a p+ doped region 34 formed in the substrate 30, a second n+ doped region 36 formed in the substrate 30, a third n+ doped region 38 formed in the substrate 30, and an n well 40 disposed in the substrate 30. The first n+ doped region 32, the p+ doped region 34, the second n+ doped region 36, and the third n+ doped region 38 are arranged laterally in the substrate 30 and isolated form each other by shallow trench isolations 42. The first n+ doped region 32 and the p+ doped region 34 are electrically connected to an anode 44, and the third n+ doped region 38 is electrically connected to a cathode 46. This type of LSCR device normally has a trigger voltage of 6 to 10 voltage, which is still too high to protect the internal circuit in many applications.
Please refer to FIG. 3. FIG. 3 is a schematic diagram of still another conventional LSCR device. As shown in FIG. 3, the LSCR device includes a p type substrate 50, a first n+ doped region 52 formed in the substrate 50, a p+ doped region 54 formed in the substrate 50, a second n+ doped region 56 formed in the substrate 50, a third n+ doped region 58 formed in the substrate 60, and an n well 60 in the substrate 50. The first n+ doped region 52, the p+ doped region 54, and the second n+ doped region 56 are arranged laterally in the substrate 50 and isolated form each other by shallow trench isolations 62. This type of SCR device has a gate structure 64 disposed on the surface of the substrate 50 between the second n+ doped region 56 and the third n+ doped region 58. The first n+ doped region 52 and the p+ doped region 54 are electrically connected to an anode 66, and the third n+ doped region 58 and the gate structure 64 are electrically connected to a cathode 68. The gate structure 64 is used to decrease the trigger voltage, providing the SCR device a trigger voltage of about 6 V. However, the trigger voltage has it limit, and this type of LSCR device requires more layout area, which is not desirable in IC design and fabrication.
As the requirement for ICs with lower supply voltage and high performance increases, an ESD protection device of lower trigger voltage without increasing the layout area is eagerly desirable.